View SC4000_1003831.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet preliminary speci?cation file under integrated curcuits 2000 sep 07 integrated curcuits SC4000 universal timeslot interchange
2000 sep 07 2 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 logic pin organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SC4000 100-pin tqfp (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SC4000 physical dimensions (all dimensions in millimeters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pll timing and clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 interrupts control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 clkfail timing and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 message channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 operation mode and configuration register setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 register access schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 i/o address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 busy (d_0) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read (d_1) (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 write (d_2) (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 terminate (d_3) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 channel bank select register [1:0] (d_[5:4]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 channel bank select register enable (d_6) (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset (d_7) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 channel specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 time-slot select [6:0] (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 port select [3:0] (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 parallel access enable (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 switch output enable (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 time-slot/channel select [6:0] (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 port select [3:0] (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 local connect enable (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 switch output enable (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 parallel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 serial data [1:8] (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 source parallel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 serial data [1:8] (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2000 sep 07 3 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 scbus clock master (c_0) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 scbus clock master arm (c_1) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 scbus primary/alternate select (c_2) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 diagnostic mode enable (c_3) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 scbus framing mode [1:0](c_[5:4]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 local bus framing mode [1:0](c_[7:6]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 master clock input frequency select [2:0] (c_[10:8]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 direct r/w to parallel access registers enable (c_11) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 message channel registered txd enable (c_12) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 message channel txd_0 or txd_1 select (c_13) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 message channel clock duty cycle select (c_14) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 message channel output disable (w/ loopback) (c_15) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scbus sd sample position (c_16) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 local bus si sample position (c_17) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scbus sd output delay enable (c_18) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 local bus so output delay enable (c_19) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scbus fsyncn sample position (c_20) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scbus fsyncn rate (c_21) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scbus sclkx2n, sclkx2na output disable(c_22) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scbus alternate (?? signals output enable (c_23) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 local bus l_clk polarity (c_24) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 local bus l_fs polarity (c_25) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 local bus l_fs position (c_[27:26]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 local bus l_clk & l_fs rate (c_28) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 local bus l_clk dpll enable (c_29) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 local bus l_clk 8.192 mhz 62.5% duty cycle (c_30) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 version/revision status (c_[39:32]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 master pll reference select [2:0] (c_[42:40]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 internal/external master pll select (c_43) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 scbus sref_8k source select [1:0] (c_[45:44]) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 scbus sref_8k output enable (c_46) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 scbus sclk 8.192 mhz 62.5% duty cycle (c_47) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 clock watchdog enable (c_48) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 microprocessor watchdog enable (c_49) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 scbus clkfail latch set polarity select (c_50) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 scbus clkfail latch debounce enable (c_51) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 frame boundary latch set delay enable (c_52) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 int_0 mask_n (c_53) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 int_0 output polarity (c_54) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 int_0 output driver (c_55) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 scbus clkfail latch (c_56) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 frame boundary latch (c_57) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2000 sep 07 4 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 internal master pll error latch (c_58) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 scbus error indicator (c_59) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 scbus clkfail latch clear_n (c_60) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 frame boundary latch clear_n (c_61) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 internal master pll error latch clear_n (c_62) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 scbus sclkx2n error latch (c_64) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 scbus sclkx2na error latch (c_65) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sclk error latch (c_66) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sclka error latch (c_67) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sclkx2n error latch clear_n (c_68) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sclkx2na error latch clear_n (c_69) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sclk error latch clear_n (c_70) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sclka error latch clear_n(c_71) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus fsyncn error latch (c_72) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus fsyncna error latch (c_73) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus clock master error latch (c_74) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus fsyncn error latch clear_n (c_76) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus fsyncna error latch clear_n (c_77) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus clock master error latch clear_n (c_78) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 scbus sref_8k ne sref_8ka error latch (c_80) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus clkfail ne clkfaila error latch (c_81) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus mc ne mca error latch (c_82) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus sd error indicator (c_83) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus sref_8k ne sref_8ka error latch clear_n (c_84) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus clkfail ne clkfaila error latch clear_n (c_85) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus mc ne mca error latch clear_n (c_86) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus sd error latch clear_n (c_87) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus sd_[15:0] error latch (c_[103:88]) (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 summary of SC4000 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 master clock/pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 scbus (mvip bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 message channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reserved bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 typical internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 typical write internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 typical read internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2000 sep 07 5 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 table 1. configuration register setup for scbus clock slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. configuration register setup for scbus clock master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. configuration register setup for scbus armed clock master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. configuration register setup for mvip clock master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. configuration register setup for mvip clock slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. scbus/mvip signals cross reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. microprocessor interface timing - intel bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. microprocessor interface timing - intel bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. microprocessor interface timing - multiplexed address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. local bus timing, 1x l_clk mode (c_28=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. local bus timing, 2x l_clk mode (c_28=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. scbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. scbus clock master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 14. scbus clock fail timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15. ref_8k_[3:0] and sref_8k timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2000 sep 07 6 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 1. destination and source switch function block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. internal master pll (c_43 = 0) function block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. external master pll (c_43 = 1) function block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. internal pll and local bus pll timing function block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. using two pins a_[1:0] for address bus interface scheme (c_11 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. using nine pins a_[8:0] for address bus interface scheme (c_11 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. microprocessor interface timing - intel bus mode (pin i_n = 0), non-multiplexed address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. microprocessor interface timing - motorola bus mode (pin i_n = 1), non-multiplexed address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. microprocessor interface timing - multiplexed address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. local bus timing, 1xl_clk mode (c_28=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. local bus timing, 2x l_clk mode (c_28=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. scbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. scbus clock master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14. scbus clock fail timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. ref_8k_[3:0] and sref_8k input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2000 sep 07 7 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 features timeslot interchange between local and expansion buses architecture optimized for call pro- cessing environments: scbus, mvip?and st-bus compatible full switching between any of: 128 local bus input si timeslots 128 local bus output so timeslots up to 2048 expansion bus sd timeslots multiple local bus speeds and formats: 2.048, 4.096 or 8.192 mb/s peb? stbus or gci supports both intel?and motorola? processor interfaces serial or parallel access to expansion bus enhanced input hysteresis threshold internal phased lock loop fast response and support for scbus clock fallback flexible local frame sync interface supports hyper channel capability (bundling) scbus message bus interface and local loopback control high availability and self-diagnostic features 5v cmos technology 100-pin tqfp package applications pc-based switching small to medium size digital switch matrices scbus/mvip interface functions digital centralized voice processing system voice/data multiplexer and exchange computer telephony interface logic pin organization d_7 d_6 d_5 d_4 d_3 d_2 d_1 d_0 a_8 a_7 a_6 a_5 a_4 a_3 a_2 a_1 a_0 ale cs_1_n cs_0_n rd_n(strb_n) wr_n(r/w_n) dack_n reset i_n(m) x_in x_out ref_8k_3(ref_8k_out) ref_8k_2(clk_in) ref_8k_1 ref_8k_0 si_3 si_2 si_1 si_0 txd_0 test int_1 int_0 (test_out_0)drq_r (test_out_1)drq_t sclkx2n sclkx2na sclk sclka sref_8k sref_8ka fsyncn fsyncna clkfail clkfaila sd_0 sd_1 sd_2 sd_3 sd_4 sd_5 sd_6 sd_7 sd_8 sd_9 sd_10 sd_11 sd_12 sd_13 sd_14 sd_15 mc mca l_clk l_fs so_3 so_2 so_1 so_0 mc_clk rxd 44 43 42 40 39 38 36 35 34 32 31 30 28 27 26 25 24 22 17 16 19 20 21 96 12 2 1 7 6 5 4 95 94 92 91 9 98 15 14 99 100 46 47 49 50 51 52 54 55 56 58 59 60 62 63 64 66 67 68 70 71 72 74 75 76 77 79 80 81 83 84 90 88 87 86 11 10 SC4000
2000 sep 07 8 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 block diagram SC4000 100-pin tqfp (top view) 128 x 2048 destination switch 128 x 2176 source switch timing dpll micro processor interface si_[3:0] so_[3:0] local bus timing clk_in ref_8k_[3:0] a_[8:0] d_[7:0] control scbus timing sd_[15:0] local connect control bus 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1819 20 2122 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 sd_13 sd_14 vdd sd_15 mc mca vss l_clk l_fs vdd so_0 so_1 so_2 vdd so_3 si_0 si_1 vss si_2 si_3 reset vss test drq_r drq_t x_out x_in vss ref_8k_0 ref_8k_1 ref_8k_2 ref_8k_3 vdd txd_0 rxd mc_clk i_n vdd int_0 int_1 cs_0_n sc_1_n vss rd_n wr_n dack_n ale a_0 a_1 vss sclka sclk vdd sclkx2na sclkx2n vss d_7 d_6 d_5 d_4 vss d_3 d_2 vdd d_1 d_0 a_8 vss a_7 a_6 a_5 vdd a_4 a_3 a_2 sd_12 sd_11 vss sd_10 sd_9 sd_8 vss sd_7 sd_6 sd_5 vdd sd_4 sd_3 sd_2 vdd sd_1 sd_0 clkfaila vss clkfail fsyncna fsyncn vss sref_8ka serf_8k SC4000 100-pin tqfp (top view)
2000 sep 07 9 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 SC4000 physical dimensions (all dimensions in millimeters) 16.00 0.40 14.00 0.20 + _ + _ 14.00 0.20 + _ 16.00 0.40 + _ + _ 0.50 + _ 0.14 + _ 0.25 0.60 + _ 0.15 0 0 - 0 0.22 0.05 ty p 10 1.00 ref 12 ref o 0.04 1.40 0.05 0.15 max 0.20 min 12 ref o
2000 sep 07 10 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 pin description pin name input/output pin number pin description d_[7:0] i/o 44,43,42,40, 39,38,36,35 (ttl bi-directional) microprocessor data bus. these bi-directional, tri-state lines allow the microprocessor to access SC4000 internal registers as well as the source/destination routing memory and parallel access registers. a_[8:0] i 34,32,31,30, 28,27,26,25,24 (ttl input) microprocessor address bus. these inputs select the internal registers used by a read or write opera- tion. normally these inputs are connected to microprocessor address lines a[8:0]. ale i 22 (ttl input) address latch enable. this input pin is tied to high in non-multiplexed mode. otherwise, in multi- plexed mode, the microprocessor address bus is latched internally on the falling edge of this signal. cs_1_n i 17 (ttl input) chip select 1. reserved for future internal hdlc controller. if unused, this pin should be connected to high. cs_0_n i 16 (ttl input) chip select 0. this active low signal selects the SC4000 for a microprocessor read or write operation. i_n or m i 12 (ttl input) microprocessor bus interface mode select. when this input is low, intel bus mode (i_n) is selected. when this input is high, motorola bus (m) mode is selected. rd_n or strb_n i 19 (ttl input) in intel bus mode (rd_n), this active low input operates with cs_0_n to configure the data bus lines d_[7:0] as output. in motorola bus mode (strb_n), this active low input operates with cs_0_n to enable a read or write operation. wr_n or r/w_n i 20 (ttl input) in intel bus mode (wr_n), when cs_0_n is active, the rising edge of wr_n is used to latch an inter- nal data register with data provided via the data bus lines d_[7:0]. in motorola bus mode (r/w_n), this r/w_n input is used to distinguish between read or write during a microprocessor access. dack_n i 21 (ttl input, pull up) dma acknowledge reserved for future internal hdlc controller. if unused, this pin should be left unconnected reset i 96 (ttl input) reset. this active high signal initializes the microprocessor interface, configuration, routing and paral- lel access registers. x_in i 2 (cmos input) crystal clock input. this pin is a cmos level input of either 2.048, 4.096, 8.192, 16.384, 32.768 or 65.536 mhz. a crystal of 16.384 mhz from x_in to x_out may also be used. x_out o 1 (cmos output) crystal clock output. ref_8k_3 or ref_8k_out i o 7 (ttl bi-directional) internal master pll (ref_8k_3). if configuration register bit c_43=0, this pin is a local 8 khz reference 3 input. external master pll (ref_8k_out). if configuration register bit c_43=1, this pin is an 8 khz reference output. ref_8k_2 or clk_in i 6 (ttl input) internal master pll (ref_8k_2). if configuration register bit c_43=0, this pin is a local 8 khz refer- ence 2 input. external master pll (clk_in). if configuration register bit c_43=1, this is a clock input from external master pll. ref_8k_1 i 5 (ttl input) local 8 khz reference 1 input. ref_8k_0 i 4 (ttl input) local 8 khz reference 0 input. si_[3:0] i 95,94,92,91 (ttl input, pull up) local bus serial input data streams. this pin can be programmed to 2.048, 4.096 or 8.1 92 mb/s data rates. txd_0 i 9 (ttl input, pull up) message channel transmit data. this pin is for the scbus message channel transmit data input line. test i 98 (ttl input) nand gate test mode enable. when in test mode (test=1) each pin except vdd/vss/x_out is nanded with the preceding pin and output at both drq_r and drq_t pins. int_1 i/o 15 (ttl bi-directional) interrupt request 1. reserved for future internal hdlc controller. if unused, this pin should be left unconnected. int_0 i/o 14 (ttl bi-directional) interrupt request 0. this pin will be asserted (controlled by c_[55:53]) if either scbus error, scbus clkfail, frame boundary or internal master pll error and int_0 unmasked (c_53 = 1).
2000 sep 07 11 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 pin description (continued) pin name input/output pin number pin description drq_r or test_out_0 o 99 (ttl output) receive dma request. this pin is reserved for a future internal hdlc controller. otherwise, in test mode (test=1), this is a nanded gate test chain 0 output. drq_t or test_out_1 o 100 (ttl output) transmit dma request. this pin is reserved for a future internal hdlc controller. otherwise, in test mode (test=1), this is a nanded gate test chain 1 output. sclkx2n i/o 46 (scbus bi-directional) scbus system clock x 2. sclkx2na i/o 47 (scbus bi-directional) scbus alternate system clock x 2. sclk i/o 49 (scbus bi-directional) scbus system clock. this can be programmed to either 2.048, 4.096 or 8.192 mhz. set c_0 = 1 to enable the sclk output driver as master mode. set c_0 = 0 to disable the sclk output driver as slave mode. sclka i/o 50 (scbus bi-directional) scbus alternate system clock. sref_8k i/o 51 (scbus bi-directional) scbus 8 khz reference. if c_46 = 1, the sref_8k output is enabled at scbus if c_46 = 0, the sref_8k output is disabled at scbus sref_8ka i/o 52 (scbus bi-directional) scbus 8 khz alternate reference. fsyncn i/o 54 (scbus bi-directional) scbus 8 khz frame synchronization signal. set c_0 = 1 to enable the fsyncn output driver as master mode. set c_0 = 0 to disable the fsyncn output driver as slave mode. fsyncna i/o 55 (scbus bi-directional) scbus 8 khz alternate frame synchronization signal. clkfail i/o 56 (scbus bi-directional) scbus system clock fail signal. clkfaila i/o 58 (scbus bi-directional) scbus alternate system clock fail signal. sd_[0:15] i/o 59,60,62,63, 64,66,67,68, 70,71,72,74, 75,76,77,79 (scbus bi-directional) these are scbus serial data streams can be programmed to 2.048, 4.096 or 8.192 mb/s data rates. mc i/o 80 (scbus bi-directional open collector) scbus message channel. mca i/o 81 (scbus bi-directional open collector) scbus alternate message channel. l_clk i/o 83 (ttl bi-directional) local bus clock output. it can be programmed to: 2.048, 4.096 or 8.192 mhz if set c_28 = 0. 4.096, 8.192 or 16.384 mhz if set c_28 = 1. l_fs i/o 84 (ttl bi-directional) local bus 8 khz frame synchronization output. s0_[3:0] i/o 90,88,87,86 (ttl bi-directional) local bus serial output data streams. it can be programmed to 2.048, 4.096 or 8.192 mb/s data rates. mc_clk i/o 11 (ttl bi-directional) message channel data clock. this pin is a 2.048 mhz output. the clock duty cycle can be programmed by c_14 bit. rxd i/o 10 (ttl bi-directional) message channel receive data. this pin is for the scbus message channel receive data output line. vdd power 8,13,29,37,48, 61,65,78,85,89 +5 volt power supply. vss power 3,18,23,33,41, 45,53,57,69,73, 82,93,97 ground. note: in test mode (test=1), every pin except vdd/vss/x_out/drq_r/drq_t is configured as input.
2000 sep 07 12 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 device overview the SC4000 universal timeslot inter- change is designed to provide the hard- ware interface to the scbus. its primary function is exchanging digital data be- tween the local bus serial port and the scbus serial port. a microprocessor interface allows the host controller to specify the timeslots and serial lines for this exchange. both the scbus and the local bus can be programmed to oper- ate at either 2.048 mb/s, 4.096 mb/s or 8.192 mb/s. as shown in figure 1 , the destination routing memory defines the local bus to scbus switch connection. there are 128 destination routing memory locations ?one for each local bus input channel. the data stored in the destination rout- ing memory selects the timeslot and scbus serial port connection for the local bus input channel. the source routing memory defines the scbus to local bus switch connection. there are 128 source routing memory locations ? one for each local bus output channel. the data stored in the source routing memory selects the time slot and scbus serial port connection for the local bus output channel. local bus channels to serial ports si and so time slot assignments framing mode si_0 and so_0 si_1 and so_1 si_2 and so_2 si_3 and so_3 2.048 mb/s ch[0:31] -> ts[0:31] ch[32:63] -> ts[0:31] ch[64:95] -> ts[0:31] ch[96:127] -> ts[0:31] 4.096mb/s ch[0:63] -> ts[0:63] ch[64:127] -> ts[0:63] 8.192 mb/s ch[0:127] -> ts[0:127]
2000 sep 07 13 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 writing to the routing memory is syn- chronized with scbus timing. so rout- ing information can be changed only on time slot boundaries. all input data is buffered in holding registers. the entire holding register is transferred to the out- put registers on a frame boundary basis. all frame-bounded time slots incur a one frame delay as they pass through the switch. switching data in this fashion supports time slot bundling. the so outputs are tri-state controlled on time slot boundaries by the source routing memory switch output enable bit. this allows so outputs from multi- ple devices to be connected to a com- mon line. the data sample position of both the scbus and the local bus can be selected for either 50% or 75% of the bit cell. in addition to switching local bus serial data to and from the scbus, the SC4000 provides a means of switching parallel data through the microprocessor inter- face to the scbus. a frame boundary in- terrupt helps control the timing of parallel data accesses. direct reading and writing of parallel access register con- tents makes for an efficient data transfer. when using direct access, the control- ling processor places the address of the target channel on the address bus. in this way, data can be read or written in a single cycle. to avoid data corruption, the application should not access the channel for a time period defined as four clocks before and four clocks after the frame boundary. the source routing memory local connect enable mode allows the switch- ing of any destination channel to any source channel without scbus intervention. this mode accommodates either serial or parallel data transfer. since data passes through the switch twice in this mode, there is a two-frame delay from input to output. diagnostic mode electrically disconnects the SC4000 from the scbus but allows access through the local bus. this mode is particularly useful for running board diagnostics without upsetting the scbus. a master clock source is required to run this mode. the SC4000 pinout anticipates a future version of the chip that includes an in- ternal hdlc controller for the message channel. to remain compatible with this and other subsequent versions of the SC4000, applications must write 0 to all ?eserved (read only)?configuration registers. figure 1. destination and source switch function block si_[3:0] d_[7:0] so_[3:0] output enable internal parallel read source destination parallel access input holding parallel o i output holding register timeslot & port output enable output holding input holding timeslot, port and local connect enable 1 of 128 source switch 1 of 128 destination switch routing memory routing memory register register register register sd_[15:0] access access enable local connect bus w/r_n
2000 sep 07 14 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 function description switching the SC4000 allows data switching through the microprocessor interface in any of the following three directions: from any local bus serial channel (si) or parallel data bus d_[7:0] input to any scbus channel (sd) output from any scbus channel (sd) input to any output of the local bus serial channel (so) or parallel data bus d_[7:0] from any of local bus serial channel (si) or parallel data bus d_[7:0] input directly through an internal local connect bus to any local bus serial channel (so) output as shown in figure 1, each input si and output so channel is mapped to one of 128 unique locations in the destination routing memory and source routing memory, respectively. so data stored in the destination or source routing mem- ory selects the timeslot and serial port of the scbus. all data is buffered through the input holding register, output hold- ing register or parallel access register for a switching matrix with one frame delay. pll timing and clock control the SC4000 provides the option of us- ing the internal master pll (c_43 = 0) or an external master pll (c_43 = 1). as shown in figure 2, the internal master pll generates a clock that is fre- quency-locked to an 8 khz reference in- put of either sref_8k or ref_8k[3:0]. when the SC4000 is enabled as scbus master (c_0 =1), a state machine inside the SC4000 uses this clock to generate sclk, sclkx2n and a ?ree-running? fsyncn signal based on the speed of the scbus and the clock frequency. the internal master pll runs free when: put into free run mode (ignoring reference input changes) by control c_[42:40] the 8 khz reference input is static ??or ? the input of x_in is less than 65.536 mhz. the internal master pll can also gener- ate an interrupt if it cannot lock the selected 8 khz reference input. figure 2. internal master pll (c_43 = 0) function block external crystal or osc c_0, c_3, c_[23:22] sclkx2n sclk 46, 47 49, 50 sref_8k 51, 52 ref_8k_[3:0] c_[42:40] c_[45:44] c_3, c_23, c_46 x_out x_in 1 2 master pll 8 k select reference scbus source select sref_8k clock master pll scbus 4, 5, 6, 7 fsyncn 54, 55 65.536 mhz programmable divider c_[10:8], c_[5:4] to internal watchdogs and scbus error detectors sclkx2na fsyncna sclka sref_8ka c_2 primary or alternate select
2000 sep 07 15 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 3 shows an external master pll implementation. the SC4000 provides the 8 khz reference output signal ref_8k_out (pin 7) to the external pll. this 8 khz reference signal is sourced from either ref_8k[1:0] or sref_8k. the output of the external pll is then routed back to the SC4000 via clk_in (pin 6). the master clock input (clk_in) frequency select at c_[10:8] would then be programmed for the external pll frequency. as shown in figure 4, the SC4000 also provides an internal clock pll and local bus pll timing control circuitry for both scbus master and slave operations. the internal clock pll is used to create the 4.096 or 8.192 mhz timing slaved to the scbus when the local bus is running faster than the scbus (i.e., 2.048 mhz at scbus, 8.096 mhz at local bus). if the scbus is faster or equal to the local bus, then the scbus clocks serve as the inter- nal clock and use to create the local bus clocks as well as message channel clock. the local bus clock pll is used to create a 2.048 mhz l_clk when: local bus framing mode c_[7:6] is set to 2.048 mb/s a 65.536 mhz clock is supplied on x_in the c_29 bit is set to one. if sclk stops transitionally such as during a clock fail condition (clkfail = 1), then the local bus clock pll runs free to generate l_clk clock. in addi- tion, the local bus so lines are tri-stated so that the network interface can con- tinue to run. interrupts control the SC4000 can interrupt the host cpu with the interrupt request signal int_0 (pin 14). this signal is configured and unmasked by configuration register bits c_55, c_54 and c_53. the interrupt sources are: c_56 scbus clkfail c_57 frame boundary c_58 internal master pll error c_59 scbus error indicator (logical ?r?of c_[67:64], c_[74:72], and c_[83:80]) the interrupts are structured this way to improve performance by allowing a sin- gle read operation (of configuration reg- ister byte 7) to determine whether the SC4000 is the source of the interrupt. each of the SC4000 interrupt sources can be individually masked. figure 3. external master pll (c_43 = 1) function block c_0, c_3, c_[23:22] sclkx2n sclk 46, 47 49, 50 sref_8k 51, 52 ref_8k_[1:0] c_[42:40] c_[45:44] c_3, c_23, c_46 master pll 8 k select reference scbus source select sref_8k 4, 5 fsyncn 54, 55 programmable divider c_[10:8], c_[5:4] to internal watchdogs and scbus error detectors sclkx2na fsyncna sclka sref_8ka c_2 primary or alternate select external pll clk_in 6 ref_8k_out 7
2000 sep 07 16 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 4. internal pll and local bus pll timing function block 11 sclk 49 c_[7:6], c_[5:4] mc_clk c_2 primary or alternate select internal pll primary or alternate select primary or alternate select sclka 50 sclkx2n 46 sclkx2na 47 fsyncn 54 fsyncna 55 x_in 2 clock 65.536 mhz internal timing control state machine local pll clock bus 84 l_fs l_clk 83 1 0 c_[7:6]=0x (2.048 mb/s) c_29=1 2.048 mhz
2000 sep 07 17 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 clkfail timing and control when an SC4000 is enabled to be clock master (c_0 = 1), the chip drives clock and frame sync signals to the scbus and pulls the clkfail line low. if the SC4000 is then disabled as clock master, the internal state machine waits for the next frame boundary and then stops driving clock and frame sync signals. instead, it drives the clkfail line high for one clock before tri-stating it (clk- fail is pulled up with 4.7k on every board). an ?rmed?clock master (c_1 = 1) contains logic that monitors the clkfail line (c_51 must be set). if clkfail is sampled high for two con- secutive clock periods, then the c_0 bit is automatically set; the armed master then begins driving clock and frame sync signals and pulls clkfail low. since the internal state machine was using the clock and frame sync signals driven by the previous master, the new master takes over without any framing error. it is as if one clock period had been stretched, as shown in figure 14. message channel interface the SC4000 is designed for use with an hdlc controller to implement the mes- sage channel interface. the interface be- tween an hdlc controller and SC4000 consists of the 2.048 mhz mc_clk (pin 11), txd_0 (pin 9) and rxd (pin 10) lines. data read from the scbus mc (pin 80) line is passed straight through the SC4000 to the rxd output. data read from txd_0 can be passed straight through the SC4000 to the mc output, or be buffered internally through a clocked register. buffering output data is controlled by c_12. when the message channel is disabled (c_15 = 1), txd_0 is looped back to the rxd to allow diagnostics to be run on the hdlc controller. operation mode and configuration register setup the SC4000 can be configured to func- tion in five different modes shown in the tables below: scbus clock slave (table 1) scbus clock master (table 2) scbus armed clock master (table 3) mvip clock master (table 4) mvip clock slave (table 5) table 6 shows signals that are cross referenced by scbus and mvip. table 1. con?uration register setup for scbus clock slave operation mode conguration register bits setup function description scbus slave c_0 = 0 scbus clock master disabled (default) c_1 = 0 scbus clock master disarmed (default) c_2 scbus primary or alternate select 0: primary scbus signals selected (default) 1: alternate scbus signals selected c_3 = 0 diagnostic mode disabled (note) c_[5:4] scbus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame c_[7:6] local bus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame note: default of all configuration register bits except c_3 are 0
2000 sep 07 18 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 table 2. con?uration register setup for scbus clock master operation mode conguration register bits setup function description scbus master c_0 = 1 scbus clock master enabled c_1 = 0 scbus clock master disarmed (default) c_2 scbus primary or alternate select 0: primary scbus signals selected (default) 1: alternate scbus signals selected c_3 = 0 diagnostic mode disabled c_[5:4] scbus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame c_[7:6] local bus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame c_[10:8] master clock input frequency select: 000 = 2.048 mhz (default), 001 = 4.096 mhz, 010 = 8.192 mhz, 011 = 16.384 mhz, 100 = 32.768 mhz, 101= 65.536 mhz, 11x =reserved c_21 = 0 scbus fsyncn rate to select one sclk period (default) c_22 scbus sclkx2n and sclkx2na output enable control 0: scbus sclkx2n and sclkx2na output enabled (default) 1: scbus sclkx2n and sclkx2na output disabled c_23 scbus alternate signals output enable control 0: scbus alternate signals output disabled (default) 1: scbus alternate signals output enabled c_[43:40] (internal/external master pll reference 8k select) internal/external master pll reference select: if c_43 = 0 select the reference for the internal master pll from c_[42:40]: 000 = free-run (default), 001/010 = free-run, 011 = sref_8k/sref_8ka, 100 = ref_8k_0, 101 = ref_8k_1, 110 = ref_8k_2, 111 = ref_8k_3 (see figure 2) if c_43 = 1 select the reference for the external master pll (output on ref_8k_out pin 7) from c_[42:40]: 000 = free-run (driven high) (default), 001/010 = free-run (driven high), 011 = sref_8k/sref_8ka, 100 = ref_8k_0, 101 = ref_8k_1, 110/111 = tri-state (z) (see figure 3) c_51 = 1 scbus clkfail latch debounce enabled
2000 sep 07 19 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 table 3. con?uration register setup for scbus armed clock master operation mode conguration register bits setup function description scbus armed master c_0 = 0 scbus clock master disabled initially c_1 = 1 scbus clock master armed. when clkfail goes high, c_0 bit will be automatically set and SC4000 becomes clock master c_2 scbus primary or alternate select 0: primary scbus signals selected (default) 1: alternate scbus signals selected c_3 = 0 diagnostic mode disabled c_[5:4] scbus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame c_[7:6] local bus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame c_[10:8] master clock input frequency select: 000 = 2.048 mhz (default), 001 = 4.096 mhz, 010 = 8.192 mhz, 011 = 16.384 mhz, 100 = 32.768 mhz, 101= 65.536 mhz, 11x =reserved c_21 = 0 scbus fsyncn rate to select one sclk period (default) c_22 scbus sclkx2n and sclkx2na output enable control 0: scbus sclkx2n and sclkx2na output enabled (default) 1: scbus sclkx2n and sclkx2na output disabled c_23 scbus alternate signals output enable control 0: scbus alternate signals output disabled (default) 1: scbus alternate signals output enabled c_[43:40] (internal/external master pll reference 8k select) internal/external master pll reference select: if c_43 = 0 select the reference for the internal master pll from c_[42:40]: 000 = free-run (default), 001/010 = free-run, 011 = sref_8k/sref_8ka, 100 = ref_8k_0, 101 = ref_8k_1, 110 = ref_8k_2, 111 = ref_8k_3 (see figure 2) if c_43 = 1 select the reference for the external master pll (output on ref_8k_out pin 7) from c_[42:40]: 000 = free-run (driven high) (default), 001/010 = free-run (driven high), 011 = sref_8k/sref_8ka, 100 = ref_8k_0, 101 = ref_8k_1, 110/111 = tri-state (z) (see figure 3) c_51 = 1 scbus clkfail latch debounce enabled
2000 sep 07 20 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 table 4. con?uration register setup for mvip clock master table 5. con?uration register setup for mvip clock slave operation mode conguration register bits setup function description mvip master c_0 = 1 mvip clock master enabled c_1 = 0 mvip clock master disarmed (default) c_2 = 0 primary scbus signals selected (default) c_3 = 0 diagnostic mode disabled (note 1) c_[5:4] =00 mvip framing mode to select only one rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) c_[7:6] local bus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame c_[10:8] master clock input frequency select: 000 = 2.048 mhz (default), 001 = 4.096 mhz, 010 = 8.192 mhz, 011 = 16.384 mhz, 100 = 32.768 mhz, 101= 65.536 mhz, 11x =reserved c_21 = 1 mvip f0/ rate to select one c4/ period c_22 = 0 mvip c4/ output enabled (default) c_23 =0 scbus alternate signals output disabled (default) c_[43:40] (internal/external master pll reference 8k select) internal/external master pll reference select: if c_43 = 0 select the reference for the internal master pll from c_[42:40]: 000 = free-run (default), 001/010 = free-run, 011 = sec_8k, 100 = ref_8k_0, 101 = ref_8k_1, 110 = ref_8k_2, 111 = ref_8k_3 (see figure 2) if c_43 = 1 select the reference for the external master pll (output on ref_8k_out pin 7) from c_[42:40]: 000 = free-run (driven high) (default), 001/010 = free-run (driven high), 011 = sec_8k, 100 = ref_8k_0, 101 = ref_8k_1, 110/111 = tri-state (z) (see figure 3) operation mode conguration register bits setup function description mvip slave c_0 = 0 mvip clock master disabled (default) c_1 = 0 mvip clock master disarmed (default) c_2 = 0 primary scbus signals selected (default) c_3 = 0 diagnostic mode disabled c_[5:4] = 00 mvip framing mode to select only one rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) c_[7:6] local bus framing mode to select one of the following rate: 0x = 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 = 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 = 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame
2000 sep 07 21 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 table 6. scbus/mvip signals cross reference scbus 26-pin connector scbus signal mvip signal mvip 40-pin connector 1 sclkx2n c4/ 31 2 gnd gnd 30, 32 3 sclk c2 35 4 sref_8k sec_8k 37 5 fsyncn f0/ 33 6 clkfail n/a n/a 7 sd_0 dsi0 8 8 gnd gnd 34 9 sd_1 dso0 7 10 sd_2 dsi1 10 11 sd_3 dso1 9 12 sd_4 dsi2 12 13 sd_5 dso2 11 14 sd_6 dsi3 14 15 gnd gnd 36 16 sd_7 dso3 13 17 sd_8 dsi4 16 18 sd_9 dso4 15 19 sd_10 dsi5 18 20 sd_11 dso5 17 21 gnd gnd 38 22 sd_12 dsi6 20 23 sd_13 dso6 19 24 sd_14 dsi7 22 25 sd_15 dso7 21 26 mc n/a n/a
2000 sep 07 22 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 register access schemes the SC4000 features two address access schemes. one is an indirect access scheme (c_11 = 0) to reduce the num- ber of pins required for the micropro- cessor address bus interface from nine to two (a_[1:0]), as shown in figure 5. the other is a combination of both indirect and direct parallel access schemes (c_11 = 1). using the combination requires that all nine microprocessor address pins (a_[8:0]) be used, as shown in figure 6. figure 5. using two pins a_[1:0] for address bus interface scheme (c_11 = 0) figure 6. using nine pins a_[8:0] for address bus interface scheme (c_11 = 1) microprocessor address data 03h high byte data register (hbdr) 02h low byte data register (lbdr) 01h internal address register (iar) 00h command/status register (csr) ffh - e0h source parallel access (31 - 0) dfh - c0h destination parallel access (31 - 0) bfh - a0h source routing memory (31 - 0) 9fh - 80h destination routing memory (31 - 0) 7fh - 0dh reserved 0ch - 00h configuration register (12 - 0) note: see bit 5 and 4 of csr to select the bank of channels a_[1:0] d_[7:0] ff - e0 source parallel access (31 - 0) df - c0 destination parallel access (31 - 0) bf - a0 source routing memory (31 - 0) 9f - 80 destination routing memory (31 - 0) 7f - 0d reserved 0c - 00 configuration register (12 - 0) address data 1ffh - 180h source parallel access (127 - 0) 17fh - 100h destination parallel access (127 - 0) ffh - 04h reserved 03h high byte data register (hbdr) 02h low byte data register (lbdr) 01h internal address register (iar) 00h command/status register (csr) note: see bit 5 and 4 of csr to select the bank of channels microprocessor a_[8:0] d_[7:0]
2000 sep 07 23 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 microprocessor interface i/o address map with direct r/w to parallel access registers disabled (c_11=0) (default) with direct r/w to parallel access register enable (c_11=1 ) command / status register (address = 0h) note: setting more than one command (read, write, terminate or reset) dur- ing an access to the command/status register is not recommended. busy (d_0) (read only) this bit is set (?? when a command that requires synchronization with the SC4000? internal state machine has been initiated. this bit clears (?? when the command is completed. the following commands require synchronization: destination routing memory write command source routing memory write command indirect parallel access destination write command indirect parallel access source read command read (d_1) (write only) setting this bit (?? initiates a read of the register pointed to by the internal address register. when the busy bit is clear (??, the contents of the register to be read are available by reading the low byte & highbyte data register. it is not necessary to clear (?? this bit after it has been set (??. note: set this bit for an indirect parallel access source read (this is the only ?ead?requiring synchronization). for reads which do not require synchro- nization, the data registers can be read immediately after writing the internal address register. write (d_2) (write only) setting this bit (?? initiates a write to the register selected by the internal address register. when the busy bit is clear (??, the contents of the target register have been updated using the data stored in the low byte & high byte data register. it is not necessary to clear (?? this bit after it has been set (??. terminate (d_3) (read/write) setting this bit (?? terminates a com- mand that requires synchronization with the SC4000? internal state ma- chine. this is necessary to complete a command when the SC4000? internal state machine has stopped running (no sclk). the command in process is completed asynchronously and the busy bit is cleared. it is necessary to clear (?? this bit after it has been set (??. note : a new command (read or write) should not be issued until after the terminate bit is cleared (??. channel bank select register [1:0] (d_[5:4]) (read/write) this field determines the bank of chan- nels that a command will affect. the channel bank select register field is combined with the internal address register to provide access to the channel specific registers (routing and parallel access). d_[5:4]) selects the bank of channels to be accessed. this field is cleared (?0? on reset. d_[5:4] = 00 -> ch. 0 - 31 d_[5:4] = 01 -> ch.32 - 63 d_[5:4] = 10 -> ch.64 - 95 d_[5:4] = 11 -> ch.96 - 127 channel bank select register enable (d_6) (write only) writing to the command register with this bit set (?? enables the channel bank select field to be changed. writing to the command register with this bit cleared (?? causes the channel bank select register field to retain its previous value. note 1: the channel bank select regis- ter may be changed during a write cycle which also initiates a read or write command. the read or write com- mand affects the register pointed to by the new value written into the channel bank select register. note 2: the channel bank select regis- ter should not be changed if the micro- processor interface is busy. note 3: the channel bank select regis- ter should not be changed during a write cycle that either sets (0->1) or clears (1->0) the terminate command. a_[1:0] register 3h high byte data register (hbdr) 2h low byte data register (lbdr) 1h internal address register (iar) 0h command / status register a_[8:0] register 1ffh:180h source parallel access register ch. 127:0 17fh:100h destination parallel access register ch. 127:0 0ffh:004h reserved 003h high byte data register (hbdr) 002h low byte data register (lbdr) 001h internal address register (iar) 000h command / status register d_[7:0] definition 0 busy (read only) 1 read command (write only) 2 write command (write only) 3 terminate command (read/write) [5:4] channel bank select register [1:0] (read/write) 6 channel bank select register enable (write only) 7 reset (read/write)
2000 sep 07 24 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 reset (d_7) (read/write) setting this bit (?? puts the SC4000 in reset and initializes the configuration, routing and parallel access registers. this command is analogous to the func- tion of the reset pin. clearing this bit (?? returns the SC4000 to normal op- eration, ready for configuration. internal address registerr (address = 01h) internal address register map low byte data register (address = 02h) high byte data register (address = 03h) d_[7:0] definition 7:0 internal address register (iar_[7:0]) iar_ [7:0] register iar_ [7:0] register ffh:80h channel spe- cific registers ffh:e0h source parallel access dfh:c0h destination parallel access bfh:a0h source routing memory 9fh:80h destination routing memory 7fh:0dh reserved 0ch:00h configuration registers d_[7:0] definition 7:0 low byte data register (lbdr_[7:0]) d_[7:0] definition 7:0 high byte data register (hbdr_[7:0])
2000 sep 07 25 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 channel specific registers the channel specific registers are divided into four groups. a group is se- lected by bits 5 through 7 of theinternal address register. iar_[7:5] 100 -> destination routing memory 101 -> source routing memory 110 -> destination parallel access 111 -> source parallel access channels within these groups are se- lected by bits 4 through 0 (iar_[4:0]) of the internal address register and bits 1 and 0 (d_[5:4] command/status regis- ter) of the channel bank select register (cbsr) channel speci? registers map d_[5:4] of command/status register (d_6 = 1) iar[7:0] cbsr_[1:0] = 00 cbsr_[1:0] = 01 cbsr_[1:0] = 10 cbsr_[1:0] = 11 iar_[7:5] ffh - e0h source parallel access iar_[4:0] = 1fh ch. 31 ch. 63 ch. 95 ch. 127 iar_[4:0] = 1eh ch. 30 ch. 62 ch. 94 ch. 126 . . . . . . . . . . iar_[4:0] = 01h ch. 1 ch. 33 ch. 65 ch. 97 iar_[4:0] = 00h ch. 0 ch. 32 ch. 64 ch. 96 iar_[7:5] dfh - c0h destination parallel access iar_[4:0] = 1fh ch. 31 ch. 63 ch. 95 ch. 127 iar_[4:0] = 1eh ch. 30 ch. 62 ch. 94 ch. 126 . . . . . . . . . . iar_[4:0] = 01h ch. 1 ch. 33 ch. 65 ch. 97 iar_[4:0] = 00h ch. 0 ch. 32 ch. 64 ch. 96 iar_[7:5] bfh - a0h source routing memory iar_[4:0] = 1fh ch. 31 ch. 63 ch. 95 ch. 127 iar_[4:0] = 1eh ch. 30 ch. 62 ch. 94 ch. 126 . . . . . . . . . . iar_[4:0] = 01h ch. 1 ch. 33 ch. 65 ch. 97 iar_[4:0] = 00h ch. 0 ch. 32 ch. 64 ch. 96 iar_[7:5] 9fh - 80h destination routing memory iar_[4:0] = 1fh ch. 31 ch. 63 ch. 95 ch. 127 iar_[4:0] = 1eh ch. 30 ch. 62 ch. 94 ch. 126 . . . . . . . . . . iar_[4:0] = 01h ch. 1 ch. 33 ch. 65 ch. 97 iar_[4:0] = 00h ch. 0 ch. 32 ch. 64 ch. 96
2000 sep 07 26 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 destination routing memoryelow byte time-slot select [6:0] (read/write) this field selects the scbus time-slot that a destination channel is routed to. 00h -> scbus time-slot 0 (default) 01h -> scbus time-slot 1 02h -> scbus time-slot 2 . . 7eh -> scbus time-slot 126 7fh -> scbus time-slot 127 destination routing memorye high byte port select [3:0] (read/write) this field selects the scbus port that a destination channel is routed to. 0h -> scbus sd_0 (default) 1h -> scbus sd_1 2h -> scbus sd_2 . . eh -> scbus sd_14 fh -> scbus sd_15 parallel access enable (read/write) this bit enables the destination parallel access channel to be output in place of the si local bus serial stream. 0 -> parallel access disabled (default) 1 -> parallel access enabled switch output enable (read/write) this bit enables the switch output to the scbus. 0 -> output disabled (default) 1 -> output enabled source routing memorye low byte time-slot/channel select [6:0] (read/write) if local connect is disabled (default) this field selects the scbus time-slot that is routed to a source channel. 00h -> scbus time-slot 0 (default) 01h -> scbus time-slot 1 02h -> scbus time-slot 2 . . 7eh -> scbus time-slot 126 7fh -> scbus time-slot 127 if local connect is enabled this field selects the destination channel that is routed to a source channel. 00h -> destination channel 0 (default) 01h -> destination channel 1 02h -> destination channel 2 . . 7eh -> destination channel 126 7fh -> destination channel 127 source routing memoryehigh byte port select [3:0] (read/write) this field selects the scbus port that is routed to a source channel. 0h -> scbus sd_0 (default) 1h -> scbus sd_1 2h -> scbus sd_2 . . eh -> scbus sd_14 fh -> scbus sd_15 if local connect is enabled this field is don? care. local connect enable (read/write) this bit enables the local connection of a destination channel to a source channel. 0 -> local connect disabled (default) 1 -> local connect enabled switch output enable (read/write) this bit enables the switch output to the local bus. 0 -> output disabled (default) 1 -> output enabled parallel access the parallel access channels can be ac- cessed two ways: indirect and direct. destination parallel access serial data [1:8] (read/write) this register contains the byte to be transmitted when destination routing memory parallel access is enabled note: when converted from parallel to serial, bit 1 is transmitted first. note : this register is cleared (?0? on reset. source parallel access serial data [1:8] (read only) this register contains the byte received from the source channel selected by the source routing memory. note : when converted from serial to parallel, bit 1 is received first. lbdr_[7:0] definition [6:0] time-slot select [6:0] 7 reserved hbdr_[7:0] definition [3:0] port select [3:0] [5:4] reserved 6 parallel access enable 7 switch output enable lbdr_[7:0] definition [6:0] time-slot/channel select [6:0] 7 reserved hdbr_[7:0] definition [3:0] port select [3:0] [5:4] reserved 6 local connect enable 7 switch output enable lbdr_[7:0] definition [7:0] serial data bit [1:8] lbdr_[7:0] definition [7:0] serial data bit [1:8]
2000 sep 07 27 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 configuration registers configuration register byte 0, iar = 00h scbus clock master (c_0) (read/write) this bit is synchronized with the master clock input enables the SC4000 to start and stop being scbus clock master. 0-> scbus clock master disabled (default) 1-> scbus clock master enabled note: with iar=00h and lbdr d_0=0 issue terminate command to asynchro- nously stop being scbus clock master when no master clock input is present (i.e dead clock) scbus clock master arm (c_1) (read/write) the process of becoming scbus clock master can be sped up by arming the SC4000 which is intended to become clock master in the event of a clock fail- ure. when a SC4000 is armed and clk- fail=1 the c_0 bit is automatically set. the SC4000 begins driving the scbus within 4 clocks of clkfail going high. 0-> scbus clock master disarmed (default) 1-> scbus clock master armed note : c_51 scbus clkfail debounce enable must be set to use this feature. scbus primary/alternate select (c_2) (read/write) the SC4000 provides alternate scbus signals for fault tolerance. this bit con- trols internal signal selection. 0->primary scbus signals selected (default) 1->alternate scbus signals selected diagnostic mode enable (c_3) (read/write) in diagnostic mode the SC4000? scbus output drivers and receivers are electri- cally disconnected from the scbus. in- ternally, the scbus outputs are looped back to their corresponding inputs. this creates a virtual scbus within the SC4000 that can be used to test thor- oughly the SC4000 without disrupting normal scbus traffic. 0->diagnostic mode disabled 1->diagnostic mode enabled (default) note 1 : diagnostic mode is enabled when the SC4000 is reset. note 2: a clock must be present at the master clock input to use this mode. scbus framing mode [1:0](c_[5:4]) (read/write) 0x -> 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 -> 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 -> 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame local bus framing mode [1:0](c_[7:6]) (read/write) 0x -> 2.048 mb/s, 256 bits/frame, 32 timeslots/frame (default) 10 -> 4.096 mb/s, 512 bits/frame, 64 timeslots/frame 11 -> 8.192 mb/s, 1024 bits/frame, 128 timeslots/frame note : if the local bus framing mode selection is for a higher data rate than that of the scbus framing mode, then a 65.536 mhz clock must be provided on x_in. configuration register byte 1, iar = 01h master clock input frequency select [2:0] (c_[10:8]) (read/write) 000-> 2.048 mhz (default) 001-> 4.096 mhz 010-> 8.192 mhz 011->16.384 mhz 100-> 32.768 mhz 101-> 65.536 mhz 110-> reserved 111-> reserved note : the master clock input may be sourced from either x_in or clk_in (see c_43). direct r/w to parallel access registers enable (c_11) (read/write) 0-> direct r/w disabled (default) 1-> direct r/w enabled note : when disabled a_[8:2] is don? care. when enabled address setup to falling edge of wr_n or strb_n is required. message channel registered txd enable ( c_12) (read/write) 0-> txd passed through onto mc (default) 1-> txd registered onto mc lbdr_[7:0] c_[7:0] definition 0 0 scbus clock master 1 1 scbus clock master arm 2 2 scbus primary/ alternate select 3 3 diagnostic mode enable [5:4] [5:4] scbus framing mode [1:0] [7:6] [7:6] local bus framing mode [1:0] lbdr_[7:0] c_[15:8] definition [2:0] [10:8] master clock input frequency select [2:0] 3 11 direct r/w to parallel access registers enable 4 12 message channel registered txd enable 5 13 message channel txd_0 or txd_1 (internal hdlc) select 6 14 message channel clock duty cycle select 7 15 message channel output disable (w/loopback)
2000 sep 07 28 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 note: when c_12=0 the hdlc con- troller must be programmed to output txd on the rising edge of mc_clk. when c_12=1 the hdlc controller must be programmed to output txd on the falling edge of mc_clk. message channel txd_0 or txd_1 select (c_13) (read/write) 0-> txd_0 external hdlc controller (default) 1-> txd_1 future internal hdlc controller note: if txd_1 is selected on an SC4000 without an internal hdlc controller all 1? will be output on mc (idle). message channel clock duty cycle select (c_14) (read/write) 0-> 50% (default) 1-> 75% (2 &4 mb/s scbus modes), 62.5% (8 mb/s scbus) note : sclkx2n must be present to select 75% when scbus is 2 mb/s. message channel output disable (w/ loopback) (c_15) (read/write) 0-> message channel output enabled (default) 1-> message channel output disabled note: when the message channel is dis- abled, txd is looped back to the rxd to allow diagnostics runs on the hdlc controller. configuration register byte 2, iar = 02h scbus sd sample position (c_16) (read/write) 0-> sample at 50% of bit cell (default) 1-> sample at 75% of bit cell note : sclkx2n must be present to select 75% sample. local bus si sample position (c_17) (read/write) 0-> sample at 50% of bit cell (default) 1-> sample at 75% of bit cell note 1: to select 75% sample,sclkx2n must be present or the local bus framing mode must be set to a data rate that is ei- ther higher or lower than the scbus framing mode. note 2: to select 75% sample (c_17=1), it is not necessary to select the l_clk rate equal to 2x (c_28=1) scbus sd output delay enable (c_18) (read/write) to avoid bus contention, enabled scbus sd outputs are delayed when coming out of tri-state. 0-> scbus sd output delay disabled (default) 1-> scbus sd output delay enabled local bus so output delay enable (c_19) (read/write) to avoid bus contention, enabled local bus so outputs are delayed when com- ing out of tri-state. 0-> local bus so output delay dis- abled (default) 1-> local bus so output delay enabled scbus fsyncn sample position (c_20) (read/write) 0-> sample at rising edge of sclk (default) 1-> sample at rising edge of sclkx2n with sclk high. scbus fsyncn rate (c_21) (read/write) this bit determines the clock by which the fsyncn signal is generated. 0 -> 1 sclk period (default) 1 -> 1 sclkx2n period note : this mode is provided for mvip compatibility. scbus sclkx2n, sclkx2na output disable(c_22) (read/write) this bit disables the sclkx2n and sclkx2na outputs when they are not required. when disabled, the outputs are tri-stated. 0-> sclkx2n and sclkx2na outputs enabled (default) 1-> sclkx2n and sclkx2na outputs disabled lbdr_[7:0] c_[23:16] definition 0 16 scbus sd sample position 1 17 local bus si sample position 2 18 scbus sd output delay enable 3 19 local bus so output delay enable 4 20 scbus fsyncn sample position 5 21 scbus fsyncn rate 6 22 scbus sclkx2n, sclkx2na output disable 7 23 scbus alternate (a) signals output enable
2000 sep 07 29 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 scbus alternate (a) signals output enable (c_23) (read/write) this bit enables the scbus alternate (?? signals output (when required). when disabled, the outputs are tri-stated. 0-> scbus alternate (?? signals output disabled (default) 1-> scbus alternate (?? signals output enabled configuration register byte 3, iar = 03h local bus l_clk polarity (c_24) (read/write) 0- > l_clk non-inverted (default) 1- > l_clk inverted local bus l_fs polarity (c_25) (read/write) 0- > l_fs non-inverted (default) 1- > l_fs inverted local bus l_fs position (c_[27:26]) (read/write) 00 -> l_fs occurs during the last clock period of the frame (default) 01 -> l_fs straddles the frame boundary 10 -> l_fs occurs during the first clock period of the frame 11 -> reserved local bus l_clk & l_fs rate (c_28) (read/write) 0 -> l_clk & l_fs equal to the local bus data rate (default) 1 -> l_clk & l_fs equal to 2 times the local bus data rate note: to select the 2x rate, sclkx2n must be present or the local bus fram- ing mode must be set to a data rate that is either higher or lower than the scbus framing mode. local bus l_clk dpll enable (c_29) (read/write) this mode is provided to maintain a continuous l_clk for network inter- faces during a clock fail condition. 0->l_clk dpll disabled (default) 1->l_clk dpll enabled note 1 : the local bus framing mode (c_[7:6]) must be set to 2.048 mb/s and a 65.536mhz clock must be supplied on x_in. note 2: when enabled l_clk will run free during an scbus clock fail condition. note 3: when the dpll enters the free- run, the local bus so lines are tri-stated. local bus l_clk 8.192 mhz 62.5% duty cycle (c_30) (read/write) 0 -> l_clk 8.192 mhz 62.5% duty cycle disabled (default) 1 -> l_clk 8.192 mhz 62.5% duty cycle enabled note : to enable l_clk 8.192 mhz 62.5% duty cycle, the local bus fram- ing mode (c_[7:6]) must be set to 8.192 mb/s and the scbus framing mode (c_[5:4]) must be set to 4.096 mb/s or 2.048 mb/s. c_28 must be set to 0. configuration register byte 4, iar = 04h version/revision status (c_[39:32]) the version/revision register is a read only register. it is intended for use to identify scxxxx devices. this field may be changed in future scxxxx designs. it is recommended that a test of this field be included in all ver- sions of firmware interface code. the initial release of the SC4000 will be version/revision = 10h configuration register 5,iar = 05h master pll reference select [2:0] (c_[42:40]) (read/write) when c_43=0 this field selects the refer- ence for the internal master pll. 000 -> free-run (default) 001 -> free-run 010 -> free-run 011 -> sref_8k 100 -> ref_8k_0 101 -> ref_8k_1 110 -> ref_8k_2 111 -> ref_8k_3 lbdr_[7:0] c_[31:24] definition 0 24 local bus l_clk polarity 1 25 local bus l_fs polarity [3:2] [27:26] local bus l_fs position [1:0] 4 28 local bus l_clk and l_fs rate 5 29 local bus l_clk dpll enable 6 30 local bus l_clk 8.192 mhz 62.5% duty cycle enable 7 31 reserved (0) (read only) lbdr_[7:0] c_[39:32] definition [3:0] [35:32] revision field (read only) [7:4] [39:36] version field (SC4000 = 1h, sc2000 = 0h) (read only) lbdr_[7:0] c_[47:40] definition [2:0] [42:40] master pll reference select [2:0] 3 43 internal/external master pll select [5:4] [45:44] scbus sref_8k source select [1:0] 6 46 scbus sref_8k output enable 7 47 scbus sclk 8.192 mhz 62.5% duty cycle enable
2000 sep 07 30 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 when c_43=1 this field selects the refer- ence for the external master pll which is output on ref_8k_out pin7. 000 ->free-run (driven high) (default) 001 ->free-run (driven high) 010 ->free-run (driven high) 011 -> sref_8k 100 -> ref_8k_0 101 -> ref_8k_1 110 -> tri-state (z) 111 -> tri-state (z) internal/external master pll select (c_43) (read/write) this bit selects the master pll to be either internal or external. 0 -> internal master pll (default) 1 -> external master pll scbus sref_8k source select [1:0] (c_[45:44]) (read/write) 00 -> ref_8k_0 (default) 01 -> ref_8k_1 10 -> ref_8k_2 11 -> ref_8k_3 scbus sref_8k output enable (c_46) (read/write) 0 -> scbus sref_8k disabled (z) (default) 1 -> scbus sref_8k enabled scbus sclk 8.192 mhz 62.5% duty cycle (c_47) (read/write) 0 -> sclk 8.192 mhz 62.5% duty cycle disabled (default) 1 -> sclk 8.192 mhz 62.5% duty cycle enabled note: the scbus framing mode (c_[5:4]) must be set to 8.192 mb/s to enable sclk 8.192 mhz 62.5% duty cycle. if enable (c_22=0) sclkx2n will be driven high. configuration register byte 6, iar = 06h clock watchdog enable (c_48) (read/write) this bit enables the clock watchdog. 0 -> clock watchdog disabled (default) 1 -> clock watchdog enabled note : when enabled, c_48 is read back a 1 until the master pll clocks for 125us (+/- 50%); then it reads back a 0. this mode is provided to allow detection of a missing pll clock. this information can then be used to take a master off the bus or to remove a secondary clock master from the fallback list. the clock watch- dog must be re-armed after each test. to re-arm, the clock watchdog c_48 must be cleared to ??and then set to ?? microprocessor watchdog enable (c_49) (read/write) this bit enables the microprocessor watchdog. 0 -> microprocessor watchdog dis- abled (default) 1 -> microprocessor watchdog enabled note: when enabled the SC4000 will be put into reset after the master pll clocks for 256 ms (+/-50%). this mode is provided to force an SC4000 off the scbus when it? control- ling microprocessor fail to reset the watchdog. each time c_49 is cleared ??and the set ??the watchdog count is reset. scbus clkfail latch set polarity select (c_50) (read/write) this bit selects the polarity of the scbus clkfail signal that will set the clkfail latch. 0 -> clkfail latch set when clkfail = 0 (default) 1 -> clkfail latch set when clkfail = 1 note 1: the clkfail polarity bit can be used to generate interrupts on both ends of a clkfail transition. the clkfail = 0 interrupt is used by the new primary clock source to determine that the tran- sition from secondary to primary has been made. the clkfail = 1 interrupt is used by a secondary clock source to determine that the primary clock source has given up the bus. a third module (neither primary or secondary) could use this interrupt to monitor the clk- fail transition and act as a system watchdog. note 2: only change clkfail polarity when clkfail latch clear_n (c_60) = 0. scbus clkfail latch debounce enable (c_51) (read/write) 0 -> clkfail latch debounce disabled (default) 1 -> clkfail latch debounce enabled note 1 : a clock must be present from the master pll to enable this feature. note 2: the debounce logic requires that the clkfail signal be sampled with the same value for two consecutive master pll clocks before it can set the clk- fail latch. lbdr_[7:0] c_[55:48] definition 0 48 clock watchdog enable 1 49 microprocessor watchdog enable 2 50 scbus clkfail latch set polarity select 3 51 scbus clkfail latch debounce enable 4 52 frame boundary latch set delay enable 5 53 int_0 mask_n 6 54 int_0 polarity 7 55 int_0 output driver configuration
2000 sep 07 31 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 frame boundary latch set delay enable (c_52) (read/write) 0 -> frame boundary latch set at frame boundary - no delay (default) 1 -> frame boundary latch set is delayed until after the input buffer to output buffer transfer is complete (4 internal clocks after frame boundary). note 1 : with direct w/r to parallel ac- cess register enabled (c_11=1), using the delayed frame boundary interrupt indicates that it is now safe to read from and write to the parallel access regis- ters. to avoid data corruption, all access must be completed 8 internal clocks prior to the next delayed frame bound- ary interrupt. note 2: the internal clock is equal to either the scbus data rate or the local bus data rate whichever is faster. int_0 mask_n (c_53) (read/write) clearing this bit(?? masks int_0. int_0 is the logical or of clkfail (c_56), frame boundary (c_57), inter- nal master pll error (c_58) latches and scbus error (c_59) indicator. 0 -> int_0 masked (default) 1 -> int_0 enabled note : the int_0 mask bit can be used to globally disable interrupt generation while the state of the latches can con- tinue to be polled through the micro- processor interface. this bit can also be used to create edge-triggered interrupts. int_0 output polarity (c_54) (read/write) 0 -> int_0 active low (default) 1 -> int_0 active high int_0 output driver (c_55) (read/write) 0 -> open collector int_0 output driver (default) 1 -> totem-pole int_0 output driver configuration register byte 7, iar = 07h scbus clkfail latch (c_56) (read only) 0 -> scbus clkfail latch clear 1 -> scbus clkfail latch set frame boundary latch (c_57) (read only) 0 -> frame boundary latch clear 1 -> frame boundary latch set internal master pll error latch (c_58) (read only) this latch is set when the internal mas- ter pll is not ?ocked?to its selected ref- erence. 0 -> internal master pll error latch clear 1 -> internal master pll error latch set scbus error indicator (c_59) (read only) c_59 is the logical or of c_[67:64], c_[74:72] and c_[83:80]. 0 -> all scbus error latches clear 1 -> one or more scbus error latches set scbus clkfail latch clear_n (c_60) (read/write) 0 -> scbus clkfail latch held clear (default) 1 -> scbus clkfail latch enabled frame boundary latch clear_n (c_61) (read/write) 0 -> frame boundary latch held clear (default) 1 -> frame boundary latch enabled internal master pll error latch clear_n (c_62) (read/write) 0 -> internal master pll error latch held clear (default) 1 -> internal master pll error latch enabled configuration register byte 8, iar = 08h scbus sclkx2n error latch (c_64) (read only) the scbus sclkx2n error latch is set when sclkx2n does not transition during the equivalent master pll clock period. 0 -> scbus sclkx2n error latch clear 1 -> scbus sclkx2n error latch set lbdr_[7:0] c_[63:56] definition 0 56 scbus clkfail latch (read only) 1 57 frame boundary latch (read only) 2 58 internal master pll error latch (read only) 3 59 scbus error indicator (read only) 4 60 scbus clkfail latch clear_n 5 61 frame boundary latch clear_n 6 62 internal master pll error latch clear_n 7 63 reserved (0) (read only) lbdr_[7:0] c_[71:64] definition 0 64 scbus sclkx2n error latch (read only) 1 65 scbus sclkx2na error latch (read only) 2 66 scbus sclk error latch (read only) 3 67 scbus sclka error latch (read only) 4 68 scbus sclkx2n error latch clear_n 5 69 scbus sclkx2na error latch clear_n 6 70 scbus sclk error latch clear_n 7 71 scbus sclka error latch clear_n
2000 sep 07 32 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 scbus sclkx2na error latch (c_65) (read only) the scbus sclkx2na error latch is set when sclkx2na does not transi- tion during the equivalent master pll clock period. 0 -> scbus sclkx2na error latch clear 1 -> scbus sclkx2na error latch set scbus sclk error latch (c_66) (read only) the scbus sclk error latch is set when sclk does not transition during the equivalent master pll clock period. 0 -> scbus sclk error latch clear 1 -> scbus sclk error latch set scbus sclka error latch (c_67) (read only) the scbus sclka error latch is set when sclka does not transition during the equivalent master pll clock period. 0 -> scbus sclka error latch clear 1 -> scbus sclka error latch set scbus sclkx2n error latch clear_n (c_68) (read/write) 0 ->scbus sclkx2n error latch held clear (default) 1 ->scbus sclkx2n error latch enabled scbus sclkx2na error latch clear_n (c_69) (read/write) 0 ->scbus sclkx2na error latch held clear (default) 1 ->scbus sclkx2na error latch enabled scbus sclk error latch clear_n (c_70) (read/write) 0 ->scbus sclk error latch held clear (default) 1 ->scbus sclk error latch enabled scbus sclka error latch clear_n(c_71) (read/write) 0 ->scbus sclka error latch held clear (default) 1 ->scbus sclka error latch enabled configuration register byte 9, iar = 09h scbus fsyncn error latch (c_72) (read only) the scbus fsyncn error latch is set when fsyncn does not transition during the equivalent master pll clock period. 0 ->scbus fsyncn error latch clear 1 ->scbus fsyncn error latch set scbus fsyncna error latch (c_73) (read only) the scbus fsyncna error latch is set when fsyncna does not transition during the equivalent master pll clock period. 0 ->scbus fsyncna error latch clear 1 ->scbus fsyncna error latch set scbus clock master error latch (c_74) (read only) the scbus clock master error latch is set when the SC4000 is configured to be clock master and the internally gener- ated frame sync signal and scbus fsyncn are not equal. this feature is provided to detect when more than one scbus device is enabled as clock master (i.e. two device driving fsyncn). 0 ->scbus clock master error latch clear 1 ->scbus clock master error latch set scbus fsyncn error latch clear_n (c_76) (read/write) 0 ->scbus fsyncn error latch held clear (default) 1 ->scbus fsyncn error latch enabled scbus fsyncna error latch clear_n (c_77) (read/write) 0 ->scbus fsyncna error latch held clear 1 ->scbus fsyncna error latch enabled scbus clock master error latch clear_n (c_78) (read/write) 0 ->scbus clock master error latch held clear (default) 1 ->scbus clock master error latch enabled configuration register byte 10, iar = 0ah ne: not equal lbdr_[7:0] c_[79:72] definition 0 72 scbus fsyncn error latch (read only) 1 73 scbus fsyncna error latch (read only) 2 74 scbus clock mas- ter error latch (read only) 3 75 reserved (0) (read only) 4 76 scbus fsyncn error latch clear_n 5 77 scbus fsyncna error latch clear_n 6 78 scbus clock master error latch clear_n 7 79 reserved (0) (read only) lbdr_[7:0] c_[87:80] definition 0 80 scbus sref_8k ne sref_8ka error latch (read only) 1 81 scbus clkfail ne clkfaila error latch (read only) 2 82 scbus mc ne mca error latch (read only) 3 83 scbus sd error indi- cator (read only) 4 84 scbus sref_8k ne sref_8ka error latch clear_n 5 85 scbus clkfail ne clkfaila error latch clear_n 6 86 scbus mc ne mca error latch clear_n 7 87 scbus sd error latch clear_n
2000 sep 07 33 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 scbus sref_8k ne sref_8ka error latch (c_80)(read only) the scbus sref_8k ne sref_8ka error latch is set when sref_8k and sref_8ka are not equal for three consecutive master pll clocks. 0 ->scbus sref_8k ne sref_8ka error latch clear 1 ->scbus sref_8k ne sref_8ka error latch set scbus clkfail ne clkfaila error latch (c_81)(read only) the scbus clkfail ne clkfaila error latch is set when clkfail and clkfaila are not equal for three consecutive master pll clocks. 0 ->scbus clkfail ne clkfaila error latch clear 1 ->scbus clkfail ne clkfaila error latch set scbus mc ne mca error latch (c_82) (read only) the scbus mc ne mca error latch is set when mc and mca are not equal. mc_clk is used to sample the comparison. 0 ->scbus mc ne mca error latch clear 1 ->scbus mc ne mca error latch set scbus sd error indicator (c_83) (read only) c_83 is the logical or of c_[103:88] 0 -> all scbus sd error latches clear 1 -> one or more scbus sd error latch set scbus sref_8k ne sref_8ka error latch clear_n (c_84)(read/write) 0 ->scbus sref_8k ne sref_8ka error latch held clear (default) 1 ->scbus sref_8k ne sref_8ka error latch enabled scbus clkfail ne clkfaila error latch clear_n (c_85)(read/write) 0 ->scbus clkfail ne clkfaila error latch held clear (default) 1 ->scbus clkfail ne clkfaila error latch enabled scbus mc ne mca error latch clear_n (c_86)(read/write) 0 ->scbus mc ne mca error latch held clear (default) 1 ->scbus mc ne mca error latch enabled scbus sd error latch clear_n (c_87)(read/write) 0 ->scbus sd error latch held clear (default) 1 ->scbus sd error latch enabled note : c_87 controls all 16 sd error latches. configuration register byte 11, iar = 0bh configuration register byte 12, iar = 0ch scbus sd_[15:0] error latch (c_[103:88]) (read only) an scbus sd error latch is set when an sd output timeslot is enabled and the internally generated sd signal and scbus are not equal. this feature is provided to detect when more than one scbus device is enabled on the same timeslot. all scbus sd error latches are enabled and cleared by c_87. note: if multiple destination channels within the same SC4000 are enabled onto the same timeslot anerror will not occur. bus contention is prevented by logically ?nding?the internal sd signals before they are output onto the scbus sd. summary of SC4000 configuration registers miscellaneous diagnostic mode enable (c_3) (read/write) direct r/w to parallel access registers enable (c_11) (read/write) SC4000 revision/version register (c_[39:32]) (read only) master clock/pll master clock input frequency select [2:0] (c_[10:8]) (read/write) master pll reference select [2:0] (c_[42:40]) (read/write) internal/external master pll select (c_43) (read/write) scbus (mvip bus) scbus clock master (c_0) (read/write) scbus clock master arm (c_1) (read/write) scbus primary/alternate select (c_2) (read/write scbus framing mode [1:0](c_[5:4]) (read/write) scbus sd sample position (c_16) (read/write) scbus sd output delay enable (c_18) (read/write) scbus fsyncn sample position (c_20) (read/write) scbus fsyncn rate (c_21) (read/write) scbus sclkx2n, sclkx2na output disable (c_22) (read/write) scbus alternate (?? signals output enable (c_23) (read/write) scbus sref_8k source select [1:0] (c_[45:44]) (read/write scbus sref_8k output enable (c_46) (read/write) scbus sclk 8.192 mhz 62.5% duty cycle (c_47) (read/write) lbdr_[7:0] c_[95:88] definition [7:0] [95:88] scbus sd_[7:0] error latch (read only) lbdr_[7:0] c_[103:96] definition [7:0] [103:96] scbus sd_[15:8] error latch (read only)
2000 sep 07 34 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 local bus local bus framing mode [1:0] (c_[7:6]) (read/write) local bus si sample position (c_17) (read/write) local bus so output delay enable (c_19) (read/write) local bus l_clk polarity (c_24) (read/write) local bus l_fs polarity (c_25) (read/write) local bus l_fs position (c_[27:26]) (read/write) local bus l_clk & l_fs rate (c_28) (read/write) local bus l_clk dpll enable (c_29) (read/write) local bus l_clk 8.192 mhz 62.5% duty cycle (c_30) (read/write) message channel message channel registered txd enable (c_12) (read/write) message channel txd_0 or txd_1 select (c_13) (read/write) message channel clock duty cycle select (c_14) (read/write) message channel output disable (w/ loopback) (c_15) (read/write) watchdog clock watchdog enable (c_48) (read/write) microprocessor watchdog enable (c_49) (read/write) interrupt scbus clkfail latch set polarity select (c_50) (read/write) scbus clkfail latch debounce enable (c_51) (read/write) frame boundary latch set delay enable (c_52) (read/write) int_0 mask_n (c_53) (read/write) int_0 output polarity (c_54) (read/write) int_0 output driver (c_55) (read/write) scbus clkfail latch (c_56) (read only) frame boundary latch (c_57) (read only) internal master pll error latch (c_58) (read only) scbus error indicator (c_59) (read only) scbus clkfail latch clear_n (c_60) (read/write) frame boundary latch clear_n (c_61) (read/write) internal master pll error latch clear_n (c_62) (read/write) scbus sclkx2n error latch (c_64) (read only) scbus sclkx2na error latch (c_65) (read only) scbus sclk error latch (c_66) (read only) scbus sclka error latch (c_67) (read only) scbus sclkx2n error latch clear_n (c_68) (read/write) scbus sclkx2na error latch clear_n (c_69) (read/write) scbus sclk error latch clear_n (c_70) (read/write) scbus sclka error latch clear_n(c_71) (read/write scbus fsyncn error latch (c_72) (read only) scbus fsyncna error latch (c_73) (read only) scbus clock master error latch (c_74) (read only) scbus fsyncn error latch clear_n (c_76) (read/write) scbus fsyncna error latch clear_n (c_77) (read/write) scbus clock master error latch clear_n (c_78) (read/write) scbus sref_8k ne sref_8ka error latch (c_80)(read only) scbus clkfail ne clkfaila error latch (c_81)(read only) scbus mc ne mca error latch (c_82)(read only) scbus sd error indicator (c_83) (read only) scbus sref_8k ne sref_8ka error latch clear_n (c_84)(read/write) scbus clkfail ne clkfaila error latch clear_n (c_85)(read/write) scbus mc ne mca error latch clear_n (c_86)(read/write) scbus sd error latch clear_n (c_87)(read/write) scbus sd_[15:0] error latch (c_[103:88]) (read only) reserved bit no use bit (c_31) (read only) no use bit (c_63) (read only) no use bit (c_75) (read only) no use bit (c_79) (read only) typical internal register access typical write internal register access 1. read command/status register and test for not busy. (note1) 2. write data into internal address reg- ister, low byte data register, and high byte data register as required. 3. write a ??to the write command bit in the command/status register. (note 4) 4. read command/status register and test for not busy. (note 2) typical read internal register access 1. read command/status register and test for not busy. (note 1) 2. write data into internal address register. 3. write a ??to the read command bit in the command/status register. (note 3 & 4)
2000 sep 07 35 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 4. read command/status register and test for not busy. (note2) 5. read contents of low byte data regis- ter and high byte data register as required. note 1: it is not necessary to test for not busy in this step if the protocol used to access the SC4000 does not allow the previous command to be completed until the command/status register indi- cates not busy. note 2: it is not necessary to test for not busy in this step if the command given does not require synchronization or if the protocol used to access the SC4000 allows a command to be com- pleted while the command/status regis- ter indicates busy. note 3: it is not necessary to execute this step if the command given does not re- quire synchronization. note 4: the channel bank select field may be changed during the same write cycle which issues a command. the command will effect the register pointed to by the new value in the channel bank select field. test the nand gate test chain is enabled by forcing the test pin ?igh? when in test mode each pin is ?anded?with the preceding pin and output at the end of chain. x_in d_0 ref_8k_0 d_1 ref_8k_1 d_2 ref_8k_2 d_3 ref_8k_3 d_4 txd_0 d_5 rxd d_6 mc_clk d_7 i_n sclkx2n int_0 sclkx2na int_1 sclk cs_0_n sclka cs_1_n sref_8k rd_n sref_8ka wr_n fsyncn dack_n fsyncna ale clkfail a_0 clkfaila a_1 sd_0 a_2 sd_1 a_3 sd_2 a_4 sd_3 a_5 sd_4 a_6 sd_5 a_7 sd_6 a_8 sd_7 sd_8 drq_r sd_9 sd_10 sd_11 sd_12 sd_13 sd_14 sd_15 mc mca l_clk l_fs so_0 so_1 so_2 so_3 si_0 si_1 si_2 si_3 reset drq_t
2000 sep 07 36 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 electrical specifications absolute maximum ratings recommended operating conditions dc electrical characteristic symbol parameter test condition min max unit t s storage temperature -65 150 v i input voltage -0.5 7 p d package power dissipation 1 symbol parameter test condition min max unit t a ambient temperature 0 70 o c v dd supply voltage 4.75 5.25 symbol parameter test condition min max unit i dd supply current 100 v ih-scbus input high voltage - scbus v il-scbus input low voltage - scbus v hys-scbus input hysteresis voltage-scbus v ih-ttl input high voltage -ttl v il-ttl input low voltage -ttl v ih-cmos input high voltage -cmos v il-cmos input low voltage -cmos v v v v v v v pad = 0v v pad = 0v v i/o = v dd or v ss v v v o c v w v v v v v v oh-scbus output high voltage -scbus v ol-scbus output low voltage -scbus v oh-ttl output high voltage-ttl v ol-ttl output low voltage-ttl v oh-cmos output high voltage-cmos v ol-cmos output low voltage-cmos i p-scbus pull-up current - scbus i p-ttl pull-up current - ttl i li/o i/o leakage current +/- 10 c i-ttl input capacitance-ttl c i-cmos input capacitance-cmos c io-scbus i/o capacitance-scbus c io-ttl output or i/o capacitance - tt co-cmos output capacitance - cmos m a m a m a v dd +0.5 v dd +0.5 v dd +0.5 i oh = -24ma i ol = 24ma i oh = -8ma i ol = 8ma i oh = -0.8ma i ol = 0.8ma 7pf 7pf 6pf 6pf 12 pf -20 -50 -130 -400 0.4 0.4 v ss + 0.1 v v dd - 0.1v 3 2.4 2.6 -0.5 1.65 +/- 0.3 2.0 -0.5 0.8 0.7 x v dd -0.5 0.3 x v dd ma
2000 sep 07 37 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 ac electrical characteristics figure 7. microprocessor interface timing - intel bus mode (pin i_n = 0), non-multiplexed address table 7. microprocessor interface timing - intel bus mode symbol parameter min typ max unit t1 cs_0_n setup to wr_n - 40 40 40 t2 wr_n pulse width t3 a_[8:0] setup to wr_n (c_11 = 1) t4 a_[1:0] setup to wr_n - (c_11 = 0) t5 a_[8:0] hold from wr_n - t6 d_[7:0] setup to wr_n - 40 t7 d_[7:0] hold from wr_n - t8 d_[7:0] float to valid delay from cs_0_n, rd_n and a_[8:0] 0 t9 d_[7:0] valid to float delay from cs_0_n or rd_n notes 1. timing measured with 100 pf load on d_[7:0]. 2. write cycle may be controlled by cs_0_n or wr_n. 3. ale = 1. cs_0_n rd_n wr_n a_[8:0] d_[7:0] t2 t3 t4 t5 t8 t9 t1 t6 t7 ns ns ns ns ns ns ns ns 50 ns 5 5 5 020
2000 sep 07 38 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 8. microprocessor interface timing - motorola bus mode (pin i_n = 1), non-multiplexed address table 8. microprocessor interface timing - intel bus mode symbol parameter min typ max unit t1 cs_0_n setup to strb_n - t2 strb_n pulse width t3 r/w_n setup to strb_n t4 r/w_n hold from strb_n - t5 a_[8:0] setup to strb_n (c_11 = 1) t6 a_[1:0] setup to strb_n - (c_11 = 0) t7 a_[8:0] hold from strb_n - t8 d_[7:0] setup to strb_n - t9 d_[7:0] hold from strb_n - t10 d_[7:0] float to valid delay from cs_0_n, strb_n and a_[8:0] t11 d_[7:0] valid to float delay from cs_0_n or strb_n 5 5 40 40 0 ns ns 40 40 ns ns ns ns ns ns ns ns 50 ns 5 5 5 020 notes 1. timing measured with 100 pf load on d_[7:0]. 2. write cycle may be controlled by cs_0_n or strb_n. 3. ale = 1. strb_n r/w_n a_[8:0] d_[7:0] t1 t2 t3 t4 t3 t4 t5 t6 t7 t8 t9 t10 t11 cs_0_n
2000 sep 07 39 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 9. microprocessor interface timing - multiplexed address table 9. microprocessor interface timing - multiplexed address symbol parameter min typ max unit t1 ale pulse width t2 a_[8:0] setup to ale t3 a_[8:0] hold from ale ale a_[8:0] t1 t2 t3 20 ns 5ns 5ns
2000 sep 07 40 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 10. local bus timing, 1xl_clk mode (c_28 = 0) table 10. local bus timing, 1x l_clk mode (c_28 = 0) symbol parameter min typ max unit t1a l_clk period (c_[7:6] = 0x) t1b l_clk period (c_[7:6] = 10) t1c l_clk period (c_[7:6] = 11) t2a l_fs delay from l_clk (c_29 = 0) t2b l_fs delay from l_clk (c_[7:6] = 0x, c_29 = 1) t3a so_[3:0] float to valid delay from l_clk - (c_19 = 0, c_29 = 0) t3b so_[3:0] float to valid delay from l_clk - (c_19 = 0, c_[7:6] = 0x, c_29 = 1) t3c so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 0x, c_29 = 0) t3d so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 0x, c_29 = 1) t3e so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 10) t3f so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 11) t4a so_[3:0] valid to valid delay from l_clk - (c_29 = 0) t4b so_[3:0] valid to valid delay from l_clk - (c_[7:6] = 0x, c_29 = 1) t5a so_[3:0] valid to float delay from l_clk - (c_29 = 0) t5b so_[3:0] valid to float delay from l_clk - (c_[7:6] = 0x, c_29 = 1) t6a si_[3:0] setup to l_clk (c_17 = 0, c_29 = 0) t6b si_[3:0] setup to l_clk (c_17 = 0, c_[7:6] = 0x, c_29 = 1) t7a si_[3:0] hold from l_clk (c_17 = 0, c_29 = 0) t7b si_[3:0] hold from l_clk (c_17 = 0, c_[7:6] = 0x, c_29 = 1) notes 1. timing measured with 100 pf load on all local bus outputs. 2. l_clk and l_fs shown with positive polarity, timing is equivalent when signals are inverted. t1 t2 t2 t2 t2 t2 t2 t3 t4 t5 t6 t7 si so l_clk l_fs l_fs l_fs frame boundary (c_[27:26]=00) (c_[27:26]=01) (c_[27:26]=10) 010ns -15 25 ns 010ns -15 25 ns 25 60 ns 10 75 ns 25 60 ns 10 30 ns 010ns -15 25 ns 010ns -15 25 ns 10 ns 25 ns 10 ns 25 ns 488 ns 244 ns 122 ns
2000 sep 07 41 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 11. local bus timing, 2x l_clk mode (c_28=1) table 11. local bus timing, 2x l_clk mode (c_28 = 1) symbol parameter min typ max unit t1a l_clk period (c_[7:6] = 0x) 244 ns t1b l_clk period (c_[7:6] = 10) 122 ns t1c l_clk period (c_[7:6] = 11) 61 ns t2a l_fs delay from l_clk - (c_29 = 0) t2b l_fs delay from l_clk - (c_[7:6] = 0x, c_29 = 1) t3a so_[3:0] float to valid delay from l_clk - (c_19 = 0, c_29 = 0) t3b so_[3:0] float to valid delay from l_clk - (c_19 = 0, c_[7:6] = 0x, c_29 = 1) t3c so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 0x, c_29 = 0) t3d so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 0x, c_29 = 1) t3e so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 10) t3f so_[3:0] float to valid delay from l_clk - (c_19 = 1, c_[7:6] = 11) t4a so_[3:0] valid to valid delay from l_clk - (c_29 = 0) t4b so_[3:0] valid to valid delay from l_clk - (c_[7:6] = 0x, c_29 = 1) t5a so_[3:0] valid to float delay from l_clk - (c_29 = 0) t5b so_[3:0] valid to float delay from l_clk - (c_[7:6] = 0x, c_29 = 1) t6a si_[3:0] setup to l_clk - (c_17 = 0, c_29 = 0) t6b si_[3:0] setup to l_clk - (c_17 = 0, c_[7:6] = 0x, c_29 = 1) t7a si_[3:0] hold from l_clk - (c_17 = 0,c_29 = 0) t7b si_[3:0] hold from l_clk - (c_17 = 0, c_[7:6] = 0x, c_29 = 1) t8a si_[3:0] setup to l_clk (c_17 = 1, c_29 = 0) t8b si_[3:0] setup to l_clk (c_17 = 1, c_[7:6] = 0x, c_29 = 1) t9a si_[3:0] hold from l_clk (c_17 = 1, c_29 = 0) t9b si_[3:0] hold from l_clk (c_17 = 1, c_[7:6] = 0x, c_29 = 1) notes 1. timing measured with 100 pf load on all local bus outputs. 2. l_clk and l_fs shown with positive polarity, timing is equivalent when signals are inverted. t1 frame boundary t2 t2 t2 t2 t2 t2 t3 t4 t5 t6 t7 t8 t9 l_clk l_fs l_fs l_fs so si (c_[27:26]=00) (c_[27:26]=01) (c_[27:26]=10) 25 ns 10 ns 25 ns 10 ns 25 ns 10 ns 25 ns 10 ns -15 25 ns 010ns -15 25 ns 010ns 10 30 ns 25 60 ns 10 75 ns 25 60 ns -15 25 ns 010ns -15 25 ns 010ns
2000 sep 07 42 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 12. scbus timing table 12. scbus timing symbol parameter min typ max unit t1a sclkx2n period (c_[5:4] = 0x) t1b sclkx2n period (c_[5:4] = 10) t1c sclkx2n period (c_[5:4] = 11) t2a sclk period (c_[5:4] = 0x) t2b sclk period (c_[5:4] = 10) t2c sclk period (c_[5:4] = 11) t3 fsyncn setup to sclk - (c_20 = 0) t4 fsyncn hold from sclk - (c_20 = 0) t5 fsyncn setup to sclkx2n - (c_20 = 1) t6 fsyncn hold from sclkx2n - (c_20 = 1) t7a sd_[15:0] float to valid delay from sclk - (c_18 = 0) t7b sd_[15:0] float to valid delay from sclk - (c_18 = 1, c_[5:4] = 0x) t7c sd_[15:0] float to valid delay from sclk - (c_18 = 1, c_[5:4] = 10) t7d sd_[15:0] float to valid delay from sclk - (c_18 = 1, c_[5:4] = 11) t8 sd_[15:0] valid to valid delay from sclk - t9 sd_[15:0] valid to float delay from sclk - frame boundary t2 t1 t3 t4 t6 t7 t8 t9 t14 t17 t18 t19 t10 t11 t12 t13 sclkx2n sclk fsyncn sd_[15:0] sd_[15:0] mc_clk txd mc rxd t16 t15 (output) (input) t5 10 ns 10 ns 10 ns 10 ns 244 ns 244 ns 122 ns 122 ns 61 ns 488 ns 015ns 015ns 015ns 25 60 ns 25 60 ns 10 30 ns
2000 sep 07 43 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 t10 sd_[15:0] setup to sclk (c_16 = 0) t11 sd_[15:0] hold from sclk (c_16 = 0) t12 sd_[15:0] setup to sclkx2n - (c_16 = 1) t13 sd_[15:0] hold from to sclkx2n - (c_16 = 1) t14 mc_clk delay from sclk t15 txd setup to mc_clk - (c_12 = 1) t16 txd hold from mc_clk - (c_12 = 1) t17 mc delay from mc_clk - (c_12 = 1) t18 mc delay from txd (c_12 = 0) t19 rxd delay from mc notes 1. timing measured with 100 pf load on all local bus outputs, 200 pf load on all scbus outputs. 2. mc timing measured with 200 pf, 470 w pull-up (4.7 k w /10). open collector low to high transitions include 15 ns + 60 ns delay from hi-z to 3 v. 3. timing is equivalent when alternate scbus signals are selected (c_2=1). symbol parameter min typ max unit 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 015ns 075ns 075ns 015ns
2000 sep 07 44 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 13. scbus clock master timing table 13. scbus clock master timing symbol parameter min typ max unit t1 sclk to sclkx2n skew t2 fsyncn delay from sclk (c_21 = 0) t3 fsyncn delay from sclkx2n - (c_21 = 1) note 1. timing measured with 200 pf load on all scbus outputs. frame boundary t1 t1 t2 t3 t3 t2 sclkx2n sclk fsyncn -5 5 ns 010ns 010ns
2000 sep 07 45 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 14. scbus clock fail timing table 14. scbus clock fail timing symbol parameter min typ max unit t1 clkfail delay from sclk - -5 5 ns t2a clkfail period (c_[5:4] = 0x) ns t2b clkfail period (c_[5:4] = 10) ns t2c clkfail period (c_[5:4] = 11) ns t3 sclkx2n, sclk, fsyncn float delay from clkfail float ns t4 sclkx2n, sclk, fsyncn valid delay from clkfail 10 ns note 1. timing measured with 200 pf load on all scbus outputs. bit 8 bit 1 bit 2 sclkx2n sclk fsyncn clkfail sd_[15:0] mc t2 t1 t3 t3 t3 t4 t4 t4 frame boundary 15 488 244 122
2000 sep 07 46 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 figure 15. ref_8k_[3:0] and sref_8k input mode timing table 15. ref_8k_[3:0] and sref_8k timing symbol parameter min typ max unit t1 ref_8k_[3:0] or sref_8k period t2 ref_8k_[3:0] or sref_8k high time t3 ref_8k_[3:0] or sref_8k low time note 1. timing measured with 200 pf load on all scbus outputs. t1 ref_8k_[3:0] t3 t2 sref_8k m s 125 100 ns 100 ns
2000 sep 07 47 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 sep 07 48 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 sep 07 49 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2000 sep 07 50 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 notes
2000 sep 07 51 philips semiconductors preliminary speci?cation universal timeslot interchange SC4000 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 70 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 02/pp 52 date of release: 2000 sep 07 document order number: 9397 750 07434

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